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MM74C922 * MM74C923 16-Key Encoder * 20-Key Encoder
October 1987 Revised April 2001
MM74C922 * MM74C923 16-Key Encoder * 20-Key Encoder
General Description
The MM74C922 and MM74C923 CMOS key encoders provide all the necessary logic to fully encode an array of SPST switches. The keyboard scan can be implemented by either an external clock or external capacitor. These encoders also have on-chip pull-up devices which permit switches with up to 50 k on resistance to be used. No diodes in the switch array are needed to eliminate ghost switches. The internal debounce circuit needs only a single external capacitor and can be defeated by omitting the capacitor. A Data Available output goes to a high level when a valid keyboard entry has been made. The Data Available output returns to a low level when the entered key is released, even if another key is depressed. The Data Available will return high to indicate acceptance of the new key after a normal debounce period; this two-key roll-over is provided between any two switches. An internal register remembers the last key pressed even after the key is released. The 3-STATE outputs provide for easy expansion and bus operation and are LPTTL compatible.
Features
s 50 k maximum switch on resistance s On or off chip clock s On-chip row pull-up devices s 2 key roll-over s Keybounce elimination with single capacitor s Last key register at outputs s 3-STATE output LPTTL compatible s Wide supply range: 3V to 15V s Low power consumption
Ordering Code:
Order Number MM74C922WM MM74C922N MM74C923WM MM74C923N Package Number M20B N18B M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagrams
Pin Assignment for DIP Pin Assignment for SOIC
Top View MM74C922
Top View MM74C922
(c) 2001 Fairchild Semiconductor Corporation
DS006037
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MM74C922 * MM74C923
Connection Diagrams
(Continued) Pin Assignment for DIP and SOIC Package
Top View MM74C923
Truth Tables
(Pins 0 through 11) Switch Position D A T A O U T (Pins 12 through 19) Switch 12 Position D A T A O U T
Note 1: Omit for MM74C922
0
1
2
3
4
5
6
7
8 Y3, X1 0 0 0 1 0
9 Y3, X2 1 0 0 1 0
10 Y3, X3 0 1 0 1 0
11 Y3, X4 1 1 0 1 0
Y1, X1 Y1, X2 Y1, X3 Y1, X4 Y2, X1 Y2, X2 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0
Y2, X3 Y2, X4 0 1 1 0 0 1 1 1 0 0
A B C D E (Note 1)
13 Y4, X2 1 0 1 1 0
14 Y4, X3 0 1 1 1 0
15 Y4, X4 1 1 1 1 0
16
17
18
19
Y4, X1 0 0 1 1 0
Y5(Note 1), X1 Y5 (Note 1), X2 Y5 (Note 1), X3 Y5 (Note 1), X4 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 0 0 1
A B C D E (Note 1)
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MM74C922 * MM74C923
Block Diagram
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MM74C922 * MM74C923
Absolute Maximum Ratings(Note 2)
Voltage at Any Pin Operating Temperature Range MM74C922, MM74C923 Storage Temperature Range Power Dissipation (P D) Dual-In-Line Small Outline Operating VCC Range VCC Lead Temperature (Soldering, 10 seconds) 260C 700 mW 500 mW 3V to 15V 18V
Note 2: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
VCC - 0.3V to V CC + 0.3V
-40C to +85C -65C to +150C
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise specified Symbol Parameter Conditions CMOS TO CMOS VT+ Positive-Going Threshold Voltage at Osc and KBM Inputs VT- Negative-Going Threshold Voltage at Osc and KBM Inputs VIN(1) Logical "1" Input Voltage, Except Osc and KBM Inputs VIN(0) Logical "0" Input Voltage, Except Osc and KBM Inputs Irp Row Pull-Up Current at Y1, Y2, Y3, Y4 and Y5 Inputs VOUT(1) Logical "1" Output Voltage VCC = 5V, IIN 0.7 mA VCC = 10V, IIN 1.4 mA VCC = 15V, IIN 2.1 mA VCC = 5V, IIN 0.7 mA VCC = 10V, IIN 1.4 mA VCC = 15V, IIN 2.1 mA VCC = 5V VCC = 10V VCC = 15V VCC = 5V VCC = 10V VCC = 15V VCC = 5V, VIN = 0.1 VCC VCC = 10V VCC = 15V VCC = 5V, IO = -10 A VCC = 10V, IO = -10 A VCC = 15V, IO = -10 A VOUT(0) Logical "0" Output Voltage VCC = 5V, IO = 10 A VCC = 10V, IO = 10 A VCC = 15V, IO = 10 A Ron Column "ON" Resistance at X1, X2, X3 and X4 Outputs ICC Supply Current Osc at 0V, (one Y low) IIN(1) IIN(0) Logical "1" Input Current at Output Enable Logical "0" Input Current at Output Enable CMOS/LPTTL INTERFACE VIN(1) VIN(0) VOUT(1) Except Osc and KBM Inputs Except Osc and KBM Inputs Logical "1" Output Voltage VCC = 4.75V VCC = 4.75V IO = -360 A VCC = 4.75V IO = -360 A 2.4 V VCC - 1.5 0.8 V V VCC = 15V, VIN = 0V -1.0 -0.005 A VCC = 5V, VO = 0.5V VCC = 10V, VO = 1V VCC = 15V, VO = 1.5V VCC = 5V VCC = 10V VCC = 15V VCC = 15V, VIN = 15V 500 300 200 0.55 1.1 1.7 0.005 4.5 9 13.5 0.5 1 1.5 1400 700 500 1.1 1.9 2.6 1.0 3.0 6.0 9.0 0.7 1.4 2.1 3.5 8.0 12.5 3.6 6.8 10 1.4 3.2 5 4.5 9 13.5 0.5 1 1.5 -2 -10 -22 1.5 2 2.5 -5 -20 -45 4.3 8.6 12.9 2.0 4.0 6.0 V V V V V V V V V V V V A A A V V V V V V mA mA mA A Min Typ Max Units
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MM74C922 * MM74C923
DC Electrical Characteristics
Symbol VOUT(0) Parameter Logical "0" Output Voltage
(Continued)
Conditions Min Typ Max 0.4 Units V
IO = -360 A VCC = 4.75V IO = -360 A
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE ISOURCE ISINK ISINK Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) VCC = 5V, VOUT = 0V, TA = 25C VCC = 10V, VOUT = 0V, TA = 25C VCC = 5V, VOUT = VCC, TA = 25C VCC = 10V, VOUT = VCC, TA = 25C 8 16 mA 1.75 3.6 mA -8 -15 mA -1.75 -3.3 mA
AC Electrical Characteristics
TA = 25C, CL = 50 pF, unless otherwise noted Symbol Parameter tpd0, tpd1 Propagation Delay Time to Logical "0" or Logical "1" from D.A. t0H, t1H Propagation Delay Time from Logical "0" or Logical "1" into High Impedance State tH0, tH1 Propagation Delay Time from High Impedance State to a Logical "0" or Logical "1" CIN COUT Input Capacitance 3-STATE Output Capacitance
(Note 3)
Conditions Min Typ 60 35 25 80 65 50 100 55 40 5 10 Max 150 80 60 200 150 110 250 125 90 7.5 Units ns ns ns ns ns ns ns ns ns pF pF
CL = 50 pF (Figure 1) VCC = 5V VCC = 10V VCC = 15V RL = 10k, CL = 10 pF (Figure 2) VCC = 5V, RL = 10k VCC = 10V, C L = 10 pF VCC = 15V RL = 10k, CL = 50 pF (Figure 2) VCC = 5V, RL = 10k VCC = 10V, CL = 50 pF VCC = 15V Any Input (Note 4) Any Output (Note 4)
Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: Capacitance is guaranteed by periodic testing.
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MM74C922 * MM74C923
Switching Time Waveforms
T1 T2 RC, T3 0.7 RC, where R 10k and C is external capacitor at KBM input.
FIGURE 1.
FIGURE 2.
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MM74C922 * MM74C923
Typical Performance Characteristics
Typical Irp vs VIN at Any Y Input Typical Ron vs VOUT at Any X Output
Typical FSCAN vs COSC
Typical Debounce Period vs CKBM
Typical Applications
Synchronous Handshake (MM74C922) Synchronous Data Entry Onto Bus (MM74C922)
The keyboard may be synchronously scanned by omitting the capacitor at osc. and driving osc. directly if the system clock rate is lower than 10 kHz
Outputs are enabled when valid entry is made and go into 3-STATE when key is released. The keyboard may be synchronously scanned by omitting the capacitor at osc. and driving osc. directly if the system clock rate is lower than 10 kHz
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MM74C922 * MM74C923
Asynchronous Data Entry Onto Bus (MM74C922)
Outputs are in 3-STATE until key is pressed, then data is placed on bus. When key is released, outputs return to 3-STATE.
Expansion to 32 Key Encoder (MM74C922)
Theory of Operation
The MM74C922/MM74C923 Keyboard Encoders implement all the logic necessary to interface a 16 or 20 SPST key switch matrix to a digital system. The encoder will convert a key switch closer to a 4(MM74C922) or 5(MM74C923) bit nibble. The designer can control both the keyboard scan rate and the key debounce period by altering the oscillator capacitor, COSE, and the key bounce mask capacitor, CMSK. Thus, the MM74C922/MM74C923's performance can be optimized for many keyboards. The keyboard encoders connect to a switch matrix that is 4 rows by 4 columns (MM74C922) or 5 rows by 4 columns (MM74C923). When no keys are depressed, the row inputs are pulled high by internal pull-ups and the column outputs sequentially output a logic "0". These outputs are open drain and are therefore low for 25% of the time and otherwise off. The column scan rate is controlled by the oscillator input, which consists of a Schmitt trigger oscillator, a 2bit counter, and a 2-4-bit decoder. When a key is depressed, key 0, for example, nothing will happen when the X1 input is off, since Y1 will remain high. When the X1 column is scanned, X1 goes low and Y1 will go low. This disables the counter and keeps X1 low. Y1 going low also initiates the key bounce circuit timing and locks out the other Y inputs. The key code to be output is a combination of the frozen counter value and the decoded Y inputs. Once the key bounce circuit times out, the data is latched, and the Data Available (DAV) output goes high. If, during the key closure the switch bounces, Y1 input will go high again, restarting the scan and resetting the key bounce circuitry. The key may bounce several times, but as soon as the switch stays low for a debounce period, the closure is assumed valid and the data is latched. A key may also bounce when it is released. To ensure that the encoder does not recognize this bounce as another key closure, the debounce circuit must time out before another closure is recognized. The two-key roll-over feature can be illustrated by assuming a key is depressed, and then a second key is depressed. Since all scanning has stopped, and all other Y inputs are disabled, the second key is not recognized until the first key is lifted and the key bounce circuitry has reset. The output latches feed 3-STATE, which is enabled when the Output Enable (OE) input is taken low.
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MM74C922 * MM74C923
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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MM74C922 * MM74C923
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N18B
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MM74C922 * MM74C923 16-Key Encoder * 20-Key Encoder
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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